Skip to main content

About David W. Parent

My research areas are low power analog design for silicon neurons for robotic applications, hafnium oxide deposition for neural interfacing, and improving student performance in introductory circuits classes. I use a virtuoso and calibre CAD flow to design fabricate (MOSIS), and test analog circuits in .5 and .18 micron CMOS technology (one day 65nm). I use thermal evaporation and a small oxygen flow to deposit hafnium oxide in our micro poressing lab. I use flipped classroom, project based learning, student entry behaviors, and directed self placement to improve student performance in classes. I also use myopenmath to develop meaningful online (automatically graded) HW assignments. Current Projects :optimize OPAMPS for low power and yield, MIS solar cell for workforce development.

Positions

Present Professor, San Jose State University Electrical Engineering
to

Curriculum Vitae



Research Interests


$
to
Enter a valid date range.

to
Enter a valid date range.

Education

to
1999 Ph.D., University of Connecticut ‐ Electrical Engineering
to
1996 M.S., University of Connecticut ‐ Electrical Engineering
to
1992 B.S., University of Connecticut ‐ Electrical Engineering
to


Contact Information

David.Parent@sjsu.edu



Publications (15)

Conference Publications (28)