"Design of a low-complexity wideband analog true-time-delay 5-beam array in 65nm CMOS" by Arjuna Madanayake

Selected Works of Sirani Mututhanthrige Perera

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Design of a low-complexity wideband analog true-time-delay 5-beam array in 65nm CMOS

International Midwest Symposium on Circuits and Systems (2017)

Arjuna Madanayake, University of Akron
Viduneth Ariyarathna, University of Akron
Nilan Udayanga, University of Akron
Leonid Belostotski, University of Calgary
Sirani K. Perera, Embry-Riddle Aeronautical University, Daytona Beach
Renato J. Cintra, Federal University of Pernambuco

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Disciplines

Computer Sciences and
Electrical and Electronics

Publication Date

August 1, 2017

DOI

10.1109/MWSCAS.2017.8053145

Citation Information

Arjuna Madanayake, Viduneth Ariyarathna, Nilan Udayanga, Leonid Belostotski, et al.. "Design of a low-complexity wideband analog true-time-delay 5-beam array in 65nm CMOS" International Midwest Symposium on Circuits and Systems (2017) p. 1204 - 1207
Available at: http://works.bepress.com/sirani-perera/4/