Synchronizers are necessary when importing signals into any clocked domain. As multiple different clocks become increasingly common on chips, synchronizers also proliferate. To achieve high performance, it is important that the system designer is aware of the timing characteristics of different synchronizers -which are non-deterministic by nature – and can choose a design to meet their system requirements. This paper presents a method for analysing and depicting behaviour of synchronizers and applies this to two recognised designs. A detailed analysis of timing boundaries of the two synchronizers is presented. The probabilistic behaviour of data cycle is then investigated. Analytical expressions for the average data cycle are also derived.