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About Zhao Zhang

My research interests include high performance computer architecture, parallel and distributed computing, and architectural support for security. My representative works include (not exclusively, and done with my students and/or collaborators):
  • "A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality" (MICRO 2000): We find out that cache misses and writebacks may incur severe DRAM row-buffer conflicts under conventional memory address mapping, and propose a simple XOR-based mapping to resolve the conflicts. The technique has been adopted in many processors and chipsets: Sun UltraSPARC IIIi Sun Gemini, AMD Geode LX, AMD Geode GX3, Mobile Intel 4 Express chipset family, NVIDIA chipset GeForce 7025/nForce 630a, and Intel Haswell i7 processor.
  • "Gaining insights into multicore cache partitioning: bridging the gap between simulation and real systems" (HPCA 2008). It is a comprehensive execution- and measurement-based study on multicore cache partitioning. The cache management method it proposes has been been used in Linux kernel for production systems.

Positions

Present Associate Professor, Iowa State University Department of Electrical and Computer Engineering
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Contact Information

2215 Coover
2520 Osborn Dr
Ames, IA 50011
515-294-2664

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Peer-Reviewed Articles (15)

Theses and Dissertations (3)

Conference Proceedings (3)