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Cryogenic to Room Temperature Effects of NBTI in High-k PMOS Devices
2011 IEEE International Integrated Reliability Workshop Final Report (IRW) (2011)
  • Richard G. Southwick, III, Boise State University
  • Shem T. Purnell, Boise State University
  • Blake A. Rapp, Boise State University
  • Ryan J. Thompson, Boise State University
  • Shane K. Pugmire, Boise State University
  • Ben Kaczer, IMEC
  • Tibor Grasser, Institute for Microelectronics Technische Universität Wien
  • William B. Knowlton, Boise State University
Abstract
We present experimental evidence that trapping mechanisms contributing to the negative bias temperature instability (NBTI) of high-k dielectric p-channel metal oxide semiconductor (pMOS) transistors are thermally activated. Device behavior during stress and recovery from 300 K down to 6 K indicate the dominance of the hole trapping mechanism commonly attributed to NBTI is reduced as temperature decreases. Further, trends in the temperature dependence of drain current shifts suggest more than one mechanism is responsible for NBTI. Specifically, below 240 K, current degradation immediately following stress is no longer observed. In fact, the opposite effect occurs, which is suggestive of electron trapping as the dominant mechanism at such temperatures.
Keywords
  • current measurement,
  • logic gates,
  • performance evaluation,
  • stress,
  • temperature measurement,
  • thermal stability
Publication Date
2011
DOI
10.1109/IIRW.2011.6142577
Citation Information
Richard G. Southwick, Shem T. Purnell, Blake A. Rapp, Ryan J. Thompson, et al.. "Cryogenic to Room Temperature Effects of NBTI in High-k PMOS Devices" 2011 IEEE International Integrated Reliability Workshop Final Report (IRW) (2011) p. 12 - 16 ISSN: 19308841
Available at: http://works.bepress.com/william_knowlton/16/