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Presentation
Candidate Subcircuits for Functional Module Identification in Logic Circuits
Proceedings of the 10th Great Lakes Symposium on VLSI
  • Jennifer L. White
  • Anthony S. Wojcik
  • Moon-Jung Chung
  • Travis E. Doom, Wright State University - Main Campus
Document Type
Conference Proceeding
Publication Date
3-1-2000
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Abstract

Recovering functional information from existing hardware is a difficult problem in design automation. However, it is an important focus for designers attempting to redesign for expanded functionality or superior performance. Often, the only reliable information available about a piece of digital hardware is the hardware itself. Documentation, even if it is available, may be outdated or incorrect. Existing procedures are able to recover the transistor-level netlist, or a gate-level netlist from an existing implementation. The next step in this process is the gate-level to module-level transformation, the focus of this paper. We have designed a technique to enumerate all of the potential modules within a gate-level netlist so that their functional equivalence to known modules may be evaluated.

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Presented at the 10th Great Lakes Symposium on VLSI, Evanston, IL, March 2-4, 2000.

DOI
10.1145/330855.332575
Citation Information
Jennifer L. White, Anthony S. Wojcik, Moon-Jung Chung and Travis E. Doom. "Candidate Subcircuits for Functional Module Identification in Logic Circuits" Proceedings of the 10th Great Lakes Symposium on VLSI (2000) p. 34 - 38 ISSN: 1581132514
Available at: http://works.bepress.com/travis_doom/33/