The importance of functional logic verification has grown considerably and spans many fields of interest, such as design verification, reengineering, and technology mapping. We present an iterative algorithm that efficiently creates and utilizes function signatures to identify functional correspondence, thus reducing the complexity of determining a semantic matching between a library circuit and a circuit under test. Previous approaches to this problem have been unable to limit certain types of correspondence between symmetric functions. The reduction of extraneous correspondences is crucial, as the verification of each match is computationally expensive. By utilizing output signatures, we will demonstrate an algorithm that is effective at handling many cases of circuit symmetry.