This paper experimentally investigates the effectiveness of embedded capacitance for reducing power-bus noise in high-speed printed circuit board designs. Boards with embedded capacitance employ closely spaced power-return plane pairs separated by a thin layer of dielectric material. In this paper, test boards with four embedded capacitance materials are evaluated. Power-bus input impedance measurements and power-bus noise measurements are presented for boards with various dimensions and layer stack ups. Unlike discrete decoupling capacitors, whose effective frequency range is generally limited to a few hundred megahertz due to interconnect inductance, embedded capacitance was found to efficiently reduce power-bus noise over the entire frequency range evaluated (up to 5 GHz).
- 5 GHz,
- Capacitance,
- Circuit Noise,
- Closely Spaced Power-Return Plane Pairs,
- Digital Circuits,
- Electromagnetic Compatibility,
- Embedded Capacitance,
- High-Speed PCB Designs,
- High-Speed Digital Designs,
- Interference Suppression,
- Layer Stack Ups,
- Power-Bus Decoupling,
- Power-Bus Input Impedance Measurements,
- Power-Bus Noise Measurements,
- Power-Bus Noise Reduction,
- Printed Circuit Board Designs,
- Printed Circuit Design,
- Printed Circuit Testing,
- Thin Dielectric Material Layer,
- Conduction Loss,
- Decoupling Capacitor,
- Embedded Capacitance (Buried Capacitance),
- Power Plane,
- Power-Bus Impedance,
- Power-Bus Noise (Delta-I Noise, Ground Bounce Noise, Simultaneous Switch Noise),
- Return Plane
Available at: http://works.bepress.com/thomas-vandoren/79/