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An Evaluation Framework for Nanotransfer Printing-Based Feature-Level Heterogeneous Integration in VLSI Circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2015)
  • Greg Leung
  • Shaodi Wang, University of California, Los Angeles
  • Andrew Pan
  • Puneet Gupta
  • Chi On Chui
Abstract
We develop an evaluation framework to assess the potential benefits of feature-level heterogeneous integration (HGI) in nanoscale VLSI circuits. We study, for the first time, the impact of HGI on circuit delay, layout area, and power by comparing the integration of 15-nm InGaAs and Ge FinFETs via nanotransfer printing with the baseline Si-only FinFET technology. To properly account for the performance, power, and area tradeoffs, we perform comprehensive evaluations, including synthesis, placement, and routing of digital circuit benchmarks. We show the circuits designed with an HGI exhibit lower delay and power due to improved device performance at the cost of larger area induced by misalignment errors. We also demonstrate that the HGI misalignment area penalties can be drastically reduced using posttransfer fin trimming. Our findings provide substantial motivation for industry to explore HGI as a technology route for the post-Si era.
Publication Date
Fall October 16, 2015
DOI
10.1109/TVLSI.2015.2477282
Citation Information
Greg Leung, Shaodi Wang, Andrew Pan, Puneet Gupta, et al.. "An Evaluation Framework for Nanotransfer Printing-Based Feature-Level Heterogeneous Integration in VLSI Circuits" IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol. 24 Iss. 5 (2015) p. 1858 - 1870 ISSN: 1557-9999
Available at: http://works.bepress.com/shaodi-wang/7/