PROCEED: A pareto optimization-based circuit-level evaluator for emerging devicesDesign Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific (2014)
Evaluation of novel devices in a circuit context is crucial to identifying and maximizing their value. We propose a new framework, PROCEED, and metrics for accurate device-circuit co-evaluation through proper optimization of digital circuit benchmarks. PROCEED assesses technology suitability over a wide operating region (MHz to GHz) by leveraging available circuit knobs (Vt assignment, power management, sizing, etc.) and improves accuracy by 3X to 115X compared to existing methods while offering orders of magnitude improvements in runtime over full physical design implementation flows. To illustrate PROCEED's capabilities, we deploy it to assess novel tunneling transistors (TFETs) compared to conventional CMOS.
Publication DateWinter January 21, 2014
Citation InformationShaodi Wang, Andrew Pan, Chi On Chui and Puneet Gupta. "PROCEED: A pareto optimization-based circuit-level evaluator for emerging devices" Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific (2014)
Available at: http://works.bepress.com/shaodi-wang/3/