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PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2015)
  • Shaodi Wang, University of California, Los Angeles
  • Andrew Pan
  • Chi On Chui
  • Puneet Gupta
Abstract
Abstract:
Evaluation of novel devices in the context of circuits is crucial to identifying and maximizing their value. We propose a new framework, Pareto optimization-based circuit-level evaluator for emerging device (PROCEED), that uses comprehensive performance, power, and area metrics for accurate device-circuit coevaluation through optimization of digital circuit benchmarks. The PROCEED assesses technology suitability over a wide operating region (megahertz to gigahertz) by leveraging available circuit knobs (threshold voltage assignment, power management, sizing, and so on). It improves the benchmark accuracy by 3x to 115x compared with the existing methods while offering orders of magnitude improvements in runtime over full physical design implementation flows. To illustrate the PROCEED's capabilities, we deploy it to assess emerging technologies, including novel tunneling field-effect transistors, compared with conventional silicon CMOS. As a further illustration, we extend PROCEED to evaluate future heterogeneous integration of varied devices onto the same silicon substrate.
Keywords
  • Logic gates,
  • Integrated circuit modeling,
  • Delays,
  • Benchmark testing,
  • Integrated circuit interconnections,
  • Silicon,
  • Performance evaluation
Publication Date
Winter February 12, 2015
DOI
10.1109/TVLSI.2015.2393852
Citation Information
Shaodi Wang, Andrew Pan, Chi On Chui and Puneet Gupta. "PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices" IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol. 24 Iss. 1 (2015) p. 192 - 205 ISSN: 1557-9999
Available at: http://works.bepress.com/shaodi-wang/2/