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4-Bit Processing Unit Design UsingVHDL Structural Modeling For Multiprocessor Architecture
IRACST – Engineering Science and Technology: An International Journal (ESTIJ) (2014)
  • Mohamed EL KHAILI
Abstract
This paper presents design concept of 4-bit Processing Unit (PU) based on 4-bit Arithmetic and Logic Unit (ALU) for multiprocessor architecture on one FPGA chip. Design methodology has been changing from schematic design to HDL based design. We use a VHDL structural and dataflow level design. Each module of the Processing Unit is divided into smaller modules. All the modules in logical unit and Arithmetic and Logic Unit (ALU) design are realized using VHDL design. Functionalities are validated through synthesis and simulation process. Processing Unit (PU) using VHDL fulfills the needs for different high performance applications such as processor for mono architecture and parallel architecture.
Keywords
  • Arithmetic and logic unit (ALU),
  • FPGA Circuits,
  • Very high scale integrated circuit Hardware Description Language
Publication Date
October, 2014
Publisher Statement
References

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Citation Information
Mohamed EL KHAILI. "4-Bit Processing Unit Design UsingVHDL Structural Modeling For Multiprocessor Architecture" IRACST – Engineering Science and Technology: An International Journal (ESTIJ) (2014)
Available at: http://works.bepress.com/sakshi-sharma/9/
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Creative Commons License
This work is licensed under a Creative Commons CC_BY-NC International License.