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Implementation of AES algorithm
International Journal of Engineering Research & Science (2016)
  • Abhinandan Aggarwal
  • Gagandeep Singh
  • Prof.(Dr.) Neelam Sharma
Abstract
Data security has become one of the most important concerns in the recent times. This has led to an increase in the importance of cryptography of the electronic data. Cryptography is the process of protecting digital information. Though there are numerous encryption systems used in security systems by various organizations, for the wider use, a particular encryption method is used as a standard. The internationally accepted and acclaimed algorithm is Advanced Encryption Standard (AES). Here in this design we are implementing the Advanced Encryption Standard (AES) with a key length of 128 bits using Verilog hardware description language (HDL).
Keywords
  • Advanced Encryption Standard (AES),
  • cryptography,
  • Cipher,
  • Encryption,
  • Field Programmable Gate Array (FPGA),
  • Hardware description language(HDL),
  • National Institute of Standards and Technology (NIST),
  • Verilog
Publication Date
April, 2016
Publisher Statement
References

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Understanding AES Mix-Columns Transformation Calculation , Kit Choy Xintong

Yang Jun Ding Jun Li Na Guo Yixiong School of Information Science and Engineering, Yunnan University Kunming, China - “FPGA based design and implementation of reduced AES algorithm”(IEEE 2010).

Deshpande, Hrushikesh S; Karande, Kailash J; Mulani, Altaaf O [ IEEE 2014 International Conference on Communications and Signal Processing (ICCSP) efficient implementation of aes algorithm on FPGA. ]

Verilog HDL: A Guide to Digital Design and Synthesis, By Samir Palnitkar.

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Citation Information
Abhinandan Aggarwal, Gagandeep Singh and Neelam Sharma. "Implementation of AES algorithm" International Journal of Engineering Research & Science (2016)
Available at: http://works.bepress.com/sakshi-sharma/3/
Creative Commons license
Creative Commons License
This work is licensed under a Creative Commons CC_BY-NC International License.