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Paper: A High Speed Low Power Adder in Multi Output Domino Logic
IJSRET (2014)
  • N Jain
  • P Gour
  • B Shrman
Abstract
Speed and power is the major constraint in modern digital design. We have to design the high speed, less number of transistor as a prime consideration. The low power carry look ahead adder using static CMOS transmission gate logic that overcomes the limitation of series connected pass transistors in the carry propagation path. In this approach it is required to find the longest critical paths in the multi-bit adders and then shortening the path to reduce the total critical path delay. The design simulation on microwind layout tool shows the worst-case delay in ns and total power consumption in microwatt range.  
Keywords
  • Adder,
  • Carry look-ahead (CLA) adders,
  • low power adder,
  • Manchester carry chain,
  • multioutput domino logic
Publication Date
December, 2014
Publisher Statement
References

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Citation Information
N Jain, P Gour and B Shrman. "Paper: A High Speed Low Power Adder in Multi Output Domino Logic" IJSRET (2014)
Available at: http://works.bepress.com/sakshi-sharma/11/
Creative Commons license
Creative Commons License
This work is licensed under a Creative Commons CC_BY-NC International License.