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Article
The effect of the digit slicing architecture on the FFT butterfly
IEEE International Conference on Information Science Signal Processing and their Application. ISSPA 2010 (2010)
  • Yazan Samir
  • Rozita Teymourzadeh
Abstract
Most communications systems tend to achieve bandwidth, power and cost efficiencies to capable to describe modulation scheme. Hence for signal modulation orthogonal frequency division multiplexing (OFDM) transceiver is introduced to cover communications demand in four generation. However high performance Fast Fourier Transforms (FFT) as a main heart of OFDM acts beyond the view. In order to achieve capable FFT, design and realization of its efficient internal structure is key issues of this research work. In this paper implementation of high performance butterfly for FFT by applying digit slicing technique is presented. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The new architecture was investigated and simulated with the MATLAB software. The Verilog HDL code in Xilinx ISE environment was derived to describe the FFT Butterfly functionality and was downloaded to Virtex II FPGA board.
Keywords
  • Digit-Slicing technique; Fast Fourier Transform (FFT); Verilog HDL; Xilinx
Publication Date
2010
Publisher Statement
IEEE
Citation Information
Yazan Samir and Rozita Teymourzadeh. "The effect of the digit slicing architecture on the FFT butterfly" IEEE International Conference on Information Science Signal Processing and their Application. ISSPA 2010 (2010): 802-805. Available at: http://works.bepress.com/rozita_teymourzadeh/10