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Toward surround gates on vertical single-walled carbon nanotube devices
Birck and NCN Publications
  • Aaron D Franklin, Birck Nanotechnology Center and School of Electrical and Computer Engineering, Purdue University
  • Robert A Sayer, Birck Nanotechnology Center and School of Mechanical Engineering, Purdue University
  • Timothy D Sands, Birck Nanotechnology Center, School of Electrical and Computer Engineering and School of Materials Engineering, Purdue University
  • Timothy Fisher, Birck Nanotechnology Center and School of Mechanical Engineering, Purdue University
  • David B Janes, Birck Nanotechnology Center and School of Electrical and Computer Engineering, Purdue University
Abstract

The one-dimensional, cylindrical nature of single-walled carbon nanotubes (SWCNTs) suggests that the ideal gating geometry for nanotube field-effect transistors (FETs) is a surround gate (SG). Using vertical SWCNTs templated in porous anodic alumina, SGs are formed using top-down processes for the dielectric/metal depositions and definition of the channel length. Surround gates allow aggressive scaling of the channel to 25% of the length attainable with a bottom-gate geometry without incurring short-channel effects. The process demonstrated here for forming SGs on vertical SWCNTs is amenable for large-scale fabrication of multinanotube FETs.

Keywords
  • FIELD-EFFECT TRANSISTOR; HIGH-PERFORMANCE ELECTRONICS; POROUS ALUMINA; ARRAYS; LITHOGRAPHY; FABRICATION; TEMPLATES; CIRCUITS; CONTACT; SILICON
Date of this Version
3-30-2009
Citation
DOI: 10.1116/1.3054266
Citation Information
Aaron D Franklin, Robert A Sayer, Timothy D Sands, Timothy Fisher, et al.. "Toward surround gates on vertical single-walled carbon nanotube devices" (2009)
Available at: http://works.bepress.com/robert_sayer/3/