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Presentation
Board Level Failure Analysis of Chip Scale Package Drop Test Assemblies
Proceedings of the 41st International Symposium on Microelectronics: Providence, RI
  • Nicholas Vickers, California Polytechnic State University - San Luis Obispo
  • Kyle Rauen, California Polytechnic State University - San Luis Obispo
  • Andrew Farris, California Polytechnic State University - San Luis Obispo
  • Jianbiao Pan, California Polytechnic State University - San Luis Obispo
Publication Date
11-2-2008
Abstract

This paper presents the failure analysis results of board level drop tests. In this study, the test vehicle was designed according to the requirements of the Joint Electron Device Engineering Council (JEDEC) drop test board. The test vehicle was assembled with 15 chip scale packages (CSPs) each having 228 daisy-chained 0.5 mm pitch solder joints using Sn-3.0 wt% Ag-0.5 wt% Cu (SAC305) lead free solder. Assemblies were drop tested using three different peak accelerations of 900 G, 1500 G, 2900 G, with 0.7 ms, 0.5 ms, and 0.3 ms pulse durations, respectively. Scanning electron microscopy (SEM) with energy dispersive spectroscopy and dye-penetrant methods were applied to investigate the failure locations and the failure modes. The failure modes and solder joint locations were mapped. Failure analysis showed that pad cratering was the most common failure mode and that this led to trace cracking on the board side. Trace cracking was the second most common failure mode. Solder joint cracking was also observed on the board side near the intermetallic layer, which was the third most common failure mode. The results imply that the solder joint is more reliable than the printed circuit board during drop test.

Citation Information
Nicholas Vickers, Kyle Rauen, Andrew Farris and Jianbiao Pan. "Board Level Failure Analysis of Chip Scale Package Drop Test Assemblies" Proceedings of the 41st International Symposium on Microelectronics: Providence, RI (2008)
Available at: http://works.bepress.com/pan/22/