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Presentation
A Parallel Sort Engine with Dynamic Memory for a Multiprocessor-on-a-Chip
Proceedings of the Fourth IASTED International Conference on Circuits, Signals, and Systems (CSS) 2006
  • Nozar Tabrizi, Kettering University
  • Nader Bagherzadeh
Document Type
Book Chapter
Publication Date
11-22-2006
Abstract

We propose a custom-designe d alternative to a memory system (generated by a memory generator) used in a 4K-word sorting accelerator which improves area efficiency by some 20%. We also show how the control unit is dramatically simplified with this n ew memory comparing with the sophisticated memory controller in the previous version. Furthermore, s ince the memory introduced here is custom designed, its size is tailored to any specific need.

Comments

ISBN: 0-88986-605-8

Rights

© 2006 ACTA Press

Citation Information
Nozar Tabrizi and Nader Bagherzadeh. "A Parallel Sort Engine with Dynamic Memory for a Multiprocessor-on-a-Chip" Proceedings of the Fourth IASTED International Conference on Circuits, Signals, and Systems (CSS) 2006 (2006) p. 169 - 174
Available at: http://works.bepress.com/nozar-tabrizi/4/