The demand for enhanced security in cryptographic systems is increasing rapidly in recent years with the development of mobile devices, such as smart phones and tablets. One of the most popular cryptographic devices that are used in these security sensitive devices is the smart card, which provides the security identification and authentication for those applications. To secure these cryptographic devices from various attacks has grown to become an attractive research topics. While recent advancements in public-key cryptographic algorithms try to eliminate or reduce the theoretical weaknesses to resist attacks, an alternative way to obtain the information of secret keys is from the physical implementation of the crypto-hardware. In this work, a random dynamic voltage scaling (RDVS) design has been proposed and implemented into an AES S-Box which is designed using asynchronous delay-insensitive logic referred to as Null convention logic (NCL). NCL utilizes symbolic completeness of expression to achieve self-timed behavior. It has been demonstrated that NCL contains all the properties to resist common forms of side-channel attack (SCA). RDVS is designed to enhance the resistance against SCA in the way of randomly changing the supply voltage so that "random noise" can be injected into the power traces to make the SCA more difficult to attack.