Carbon Nanotube FET technology is a new promising technology for high speed digital applications. This paper investigates optimizing analog circuits architecture to take advantage of this technology in mixed mode ICs. It was found through simulations that the optimum topology for high-bandwidth analog circuits is obtained by using an architecture which avoids loading by the high CNFET gate capacitance in the main signal path at high impedance points. Low junction capacitances of CNFET and high transconductance (gm) compared to silicon MOSFET indicates that high gain-bandwidth can be obtained by using CNFET. Simulations indicate low voltage operation (0.5 V) is possible using CNFET technology and also high temperature operation ( > 200 C) is possible. Monte-Carlo simulations indicate that device matching of important CNFET parameters such as nanotube diameter, channel length, source/drain doping are important to get consistent results.
- Analog,
- Carbon Nanotube FET,
- Channel Length,
- Digital Applications,
- Gate Capacitance,
- High Bandwidth,
- High Gain,
- High Impedance,
- Junction Capacitances,
- Low Voltage Operation,
- Mixed Mode,
- Monte Carlo Simulation,
- Nanotube Diameters,
- Optimum Topologies,
- Performance Assessment,
- Signal Paths,
- Silicon MOSFET,
- Capacitance,
- Carbon Nanotubes,
- High Temperature Operations,
- Lakes,
- MESFET Devices,
- Semiconducting Silicon Compounds,
- Technology,
- Analog Circuits,
- Circuits
Available at: http://works.bepress.com/minsu-choi/80/