Article
On-Chip Aging Prediction Circuit in Nanometer Digital Circuits
Proceedings of the International SoC Design Conference (2014, Jeju, South Korea)
Abstract
In nanometer technology, accurate circuit aging prediction of MOSFET digital circuits caused by aging phenominon is one of the most critical issues for more reliable adaptive tuning system design. This paper proposes a new on-chip aging sensor circuit to predit and detect a circuit failure caused by BTI and HCI aging effects on digital circuits. The proposed circuit is based on timing warning windows to warn against a guardband violation of sequential circuits, and generates three warning bits right before circuit failures occur.
Meeting Name
International SoC Design Conference: ISOCC (2014: Nov. 3-6, Jeju, South Korea)
Department(s)
Electrical and Computer Engineering
Sponsor(s)
IC Design Education Center (IDEC)
Comments
This work was supported by IC Design Education Center (IDEC).
Keywords and Phrases
- Digital Circuits,
- Integrated Circuits,
- MOSFET Devices,
- Programmable Logic Controllers,
- Adaptive Tuning,
- Aging Effects,
- Circuit Aging,
- Circuit Failures,
- Critical Issues,
- Guard-Band,
- Nanometer Technology,
- Sensor Circuit,
- Timing Circuits,
- Aging Effect,
- Aging Sensor,
- Guardband Violation
International Standard Book Number (ISBN)
978-1479951260; 978-1479951277
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2014 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
11-1-2014
Publication Date
01 Nov 2014
Disciplines
Citation Information
Byunghyun Jang, Jin Kyung Lee, Minsu Choi and Kyung Ki Kim. "On-Chip Aging Prediction Circuit in Nanometer Digital Circuits" Proceedings of the International SoC Design Conference (2014, Jeju, South Korea) (2014) p. 68 - 69 Available at: http://works.bepress.com/minsu-choi/77/