In this work, a novel asynchronous combinational S-Box (substitution box) design for AES (Advanced Encryption Standard) cryptosystems is proposed and validated. The S-Box is considered as the most critical component in AES crypto-circuits since it consumes the most power and leaks the most information against side-channel attacks. The proposed design is based on a delay-insensitive logic paradigm known as Null Convention Logic (NCL). The proposed NCL S-Box provides considerable benefits over existing designs since it consumes less power therefore suitable for energy-constrained mobile crypto-applications. It also emits less noise and has flatter power peaks therefore leaks less information against side-channel attacks such as differential power/noise analysis. Functional verification, analog simulation and power measurement of NCL S-Box have been done using Mentor Graphics EDA (Electronic Design Automation) tools to assure low-power side-channel attack-resistant operation of the proposed clock-free AES S-Box design.
- Advanced Encryption Standard,
- Analog Simulations,
- Critical Component,
- Cryptosystems,
- Electronic Design Automation,
- Energy-Constrained,
- Functional Verification,
- Logic Paradigm,
- Low Power,
- Mentor Graphics,
- Null Convention Logic,
- Power Measurement,
- S-Box Design,
- Side Channel Attack (SCA),
- Substitution Boxes,
- Computer Aided Design,
- Differentiating Circuits,
- Lakes,
- Network Security,
- Standards,
- Cryptography,
- Differential Power/Noise Analysis,
- Power/Noise Measurement,
- Security,
- Substitution Box (S-Box)
Available at: http://works.bepress.com/minsu-choi/66/