In this work, a novel model-based latency/area measurement and optimization method for the newly proposed Asynchronous Nanowire Reconfigurable Crossbar Architecture (ANRCA) is presented and validated. ANRCA is based on a self-timed logic referred to as the Null Convention Logic (NCL). Since there is no global clocking and clock distribution network, all failure modes related to timing will be either eliminated or relaxed. The proposed architecture is anticipated to have higher manufacturability and robustness that are critical factors in nanoscale systems due to nondeterministic nature of nanoassembly. In order to facilitate efficient programming and flexible reconfiguration, a new hierarchical reconfigurable architecture for ANRCA is also proposed. Various configurable logic block structures have been considered and also their programming and reconfiguration issues are discussed. The proposed measurement and optimization method can be used to estimate area and latency measurements for different configurable logic blocks and also applied to find the optimal structure for the given arbitrary logic to map. As a case study, a full adder (i.e., combinational logic block) with input and output registrations (i.e., sequential elements) has been implemented on the proposed configurable logic block structures to validate the proposed measurement and optimization method.