SoCs are in general built with embedded IP cores, each of which is procured from different IP providers with no prior information on known-good-yield (KGY). In practice, partial testing is a practical choice for assuring the yield of the product under the stringent time-to-market requirements. Therefore, a proper sampling technique is a key to high confidence testing and cost effectiveness. Based on previous research, this paper proposes a novel statistical testing technique for increasingly hybrid integrated systems fabricated on a single silicon die with no a-priori empirical yield data. This problem is referred to as the unknown-good-yield (UKGY) problem. The proposed testing method, referred to as regressive testing (RegT) in this paper, exploits another way around by using parameters (referred to as assistant variables (AV)) that are employed to evaluate the yields of randomly sampled SoCs and thereby estimating the good yield by using a regression analysis method with regard to confidence intervals. Numerous simulations are conducted to demonstrate the efficiency and effectiveness of the proposed RegT in comparison to characterization-based testing methods.