Modulo 2n + 1 multiplier is one of the critical components in the area of data security applications such as International Data Encryption Algorithm (IDEA), digital signal processing, and fault-tolerant systems that demand high reliability and fault tolerance. Transient faults caused by electrical noise or external interference are resulting in soft errors which should be detected online. The effectiveness of the residue codes in the self-checking implementation of the modulo multipliers has been rarely explored. In this paper, an efficient hardware implementation of the self-checking modulo 2n + 1 multiplier is proposed based on the residue codes. Different check bases in the form 2c - 1 or 2c + 1 (c ∈ N) are selected for various values of the input operands. In the implementation of the modulo generators and modulo multipliers, novel multiplexor-based compressors are applied for efficient modulo 2n + 1 multipliers with less area and lower power consumption. In the final addition stage of the modulo multipliers and modulo generators, efficient sparse-tree-based inverted end around carry adders are used. The proposed architecture is capable of online detecting errors caused by faults on a single gate at a time. The experimental results show that the proposed self-checking modulo 2n + 1 multipliers have less area overhead and low performance penalty.