Cryptographic algorithms such as International Data Encryption Algorithm(IDEA) have found various applications in secure transmission of the data in networked instrumentation and distributed measurement systems. Modulo 2n + 1 multiplier and squarer play a pivotal role in the implementation of such crypto-algorithms. In this work, an efficient hardware design of the IDEA (International Data Encryption Algorithm) using novel modulo 2n + 1 multiplier and squarer as the basic modules is proposed for faster, smaller and low-power IDEA hardware circuits. Novel hardware implementation of the modulo 2n + 1 multiplier is shown by using the efficient compressors and sparse tree based inverted end around carry adders is given. The novel modules are applied on IDEA algorithm and the resulting implementation is compared both qualitatively and quantitatively with the IDEA implementation using the existing multiplier/squarer implementations. Experimental measurement results show that the proposed design is faster and smaller and also consume less power than similar hardware implementations making it a viable option for efficient hardware designs.