A novel Asynchronous AES Round Function design is proposed in this paper, which offers increased Side-Channel Attack (SCA) resistance by combining the advantages of dual rail encoding and clock free operation. The design is based on a Delay Insensitive (DI) logic paradigm known as Null Convention Logic. By reducing switching activity and thereby Signal-to-Noise (SNR) ratio, the proposed design leaks far less side channel information than traditional approaches and this feature boosts SCA resistance of this approach. Functional verification and WASSO analysis simulations were carried out on both synchronous approach and the proposed NCL based approach using Xilinx simulation tools to validate the claims related to benefits of employing this novel dual rail design approach.