Article
Asynchronous Circuit Design using New High Speed NCL Gates
Proceedings of the International SoC Design Conference (2014, Jeju, South Korea)
Abstract
The delay-insensitive Null Convention Logic (NCL) as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level topologies of conventional NCL gates have weakness of logic speed, area overhead or wire complexity. Therefore, this paper proposes a new NCL gates designed at transistor level for high-speed, low area overhead. A 4 x 4 multiplier using the proposed NCL gates has been compared to the multiplier using conventional NCL gates in terms of delay, area and energy consumption.
Meeting Name
International SoC Design Conference: ISOCC (2014: Nov. 3-6, Jeju, South Korea)
Department(s)
Electrical and Computer Engineering
Sponsor(s)
IC Design Education Center (IDEC)
Comments
This work was supported by IC Design Education Center (IDEC).
Keywords and Phrases
- Asynchronous Sequential Logic,
- Design,
- Differentiating Circuits,
- Energy Utilization,
- Formal Logic,
- Integrated Circuit Manufacture,
- Multiplying Circuits,
- Area Overhead,
- Asynchronous Circuit Design,
- Asynchronous Circuit,
- Asynchronous Logic Design,
- Multiplier,
- NCL,
- Null Convention Logic,
- Transistor Level,
- Logic Circuits,
- Delay Insensitive Model
International Standard Book Number (ISBN)
978-1479951260; 978-1479951277
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2014 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
11-1-2014
Publication Date
01 Nov 2014
Disciplines
Citation Information
Minsu Choi, Byung-Ho Kang, Yong-Bin Kim and Kyung Ki Kim. "Asynchronous Circuit Design using New High Speed NCL Gates" Proceedings of the International SoC Design Conference (2014, Jeju, South Korea) (2014) p. 13 - 14 Available at: http://works.bepress.com/minsu-choi/16/