"Design, Implementation and Analysis of an Adder by Lander and Fisher" by Manfred Minimair

Selected Works of Manfred Minimair

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Unpublished Paper

Design, Implementation and Analysis of an Adder by Lander and Fisher

RISC Technical Report (1995)

Manfred Minimair, Seton Hall University

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Abstract

An addition circuit by Ladner and Fisher is analysed. Moreover the implementation of an instance of this adder capable of adding two numbers of 8-bit length was timed. The layout of this circuit was done on an FPGA by Atmel.

Keywords

adder,
FPGA circuit

Disciplines

VLSI and Circuits, Embedded and Hardware Systems

Publication Date

March, 1995

Citation Information

Manfred Minimair. "Design, Implementation and Analysis of an Adder by Lander and Fisher" RISC Technical Report (1995)
Available at: http://works.bepress.com/minimair/24/