Nanotechnology enables future advancements in integrated circuitry’s miniaturization, energy and cost efficiency, and capabilities. However, a popular, chemically assembled electronic nanotechnology (CAEN) has a high rate of defects that negates these benefits of the nanofabric. To address this challenge, we propose a testing technique that maximizes the yield from a nanofabric while minimizing the testing overhead. In contrast, traditional testing techniques, for example, the ones employed in field programable gate array (FPGA) applications, assume a low defect rate and fail to achieve high effectiveness when applied to testing nanofabrics. In this chapter, we propose a novel approach to testing a nanofabric that includes new testing configurations, test-set optimization methodology, and design of customized configuration, which provide a reduction in testing time while enhancing the utilization of the nanofabric. Part of the proposed scheme is a recovery procedure that further increases the utilization of nanoblocks at the expense of testing time. The proposed procedure tests all the components in parallel and identifies the defective nanoblocks in a nanofabric. A defect map is generated to aid logic function implementation in a nanofabric. The proposed technique results in less number of test configurations compared to other proposed methods and a significant reduction in the test time.