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Carry Select Adder Using Common Boolean Logic
International Journal of Advanced Trends in Engineering, Science and Technology (2016)
  • J. Bhavyasree, AITS, Kadapa, India
  • K. Pravallika, AITS, Kadapa, India
  • O. Homakesav, AITS, Kadapa, India
  • S. Saleem, AITS, Kadapa, India
In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSLA) is one of the fastest adders used in many data- processing processors. The structure of CSLA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate – level modification is used in order to reduce the area, delay and power of CSLA. Based on the modifications, 8-bit, 16-bit, 32-bit and 64-bit architectures of CSLA are designed and compared. In this paper, conventional CSLA is compared with Modified Carry select adder (MCSLA), Regular Square Root CSLA (SQRT CSLA), Modified SQRT CSLA and Proposed SQRT CSLA in terms of area, delay and power consumption. The result analysis shows that the proposed structure is better than the conventional CSLA.
  • Adder,
  • Carry select Adder (CSLA),
  • Modified CSLA (MCSLA),
  • Square Root CSLA (SQRT CSLA),
  • Data rocessing processors
Publication Date
Winter December 25, 2016
Publisher Statement
National Conference on Emerging Trends in Information, Digital & Embedded Systems(NC’e-TIDES-2016)
International Journal of Advanced Trends in Engineering, Science and Technology
Year: 2016 | Volume: 4 | Issue: 1 | Page No.: 185-189

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Citation Information
J. Bhavyasree, K. Pravallika, O. Homakesav and S. Saleem. "Carry Select Adder Using Common Boolean Logic" International Journal of Advanced Trends in Engineering, Science and Technology Vol. 4 Iss. 1 (2016) p. 185 - 189
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