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Implementation of 16-Bit Area Efficient Ling Carry Select Adder
International Journal of Advanced Information Science and Technology (2016)
  • P. Nithin, SRKR Engineering College, Bhimavaram, India
  • N. Udaya kumar, SRKR Engineering College, Bhimavaram, India
  • K. Bala Sindhuri, SRKR Engineering College, Bhimavaram, India
Abstract
Parallel Prefix Adders plays a prominent role in Digital Combinational Circuits. The basic function of Adder in Arithmetic and Logical Unit (ALU) is an addition. It is also used in Multipliers which results in decrease or increase of Delay that depends on the architecture of adder. Area and power are other factors which really makes the adder effective. The high-performance digital adder with reduced area and low power consumption is an important design constraint for modern advanced processors. So, low power adders are also a need for today’s VLSI industry. This paper focuses on the operation of parallel Prefix Adders of 16bit Brent-kung and Ling adder.
Keywords
  • Parallel prefix adder,
  • Ripple Carry Adder (RCA),
  • Carry Select Adder (CSLA),
  • Carry Look Ahead (CLA) Brent-Kung (BK),
  • Ling adders (LA)
Publication Date
Spring September 26, 2016
DOI
10.15693/ijaist/2016.v5i9.57-63
Publisher Statement
International Journal of Advanced Information Science and Technology
Year: 2016 | Volume: 5 | Issue: 9 | Page No.: 57-63


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Citation Information
P. Nithin, N. Udaya kumar and K. Bala Sindhuri. "Implementation of 16-Bit Area Efficient Ling Carry Select Adder" International Journal of Advanced Information Science and Technology Vol. 5 Iss. 9 (2016) p. 57 - 63 ISSN: 2319-2682
Available at: http://works.bepress.com/kiratpalsingh/77/
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This work is licensed under a Creative Commons CC_BY-NC International License.