Skip to main content
Article
Low Power & High Speed Carry Select Adder Design Using Verilog
IOSR Journal of VLSI and Signal Processing (2016)
  • Somashekhar Malipatil, Bharat Institute of Engineering & Technology, Ibrahimpatnam, Hyderabad
  • R. Basavaraju, Bharat Institute of Engineering & Technology, Ibrahimpatnam, Hyderabad
  • Praveen kumar Nartam, Bharat Institute of Engineering & Technology, Ibrahimpatnam, Hyderabad
Abstract
The binary addition is the basic arithmetic operation in digital circuits and it became essential in most of the digital systems including ALU, microprocessors and DSP. Adders are the basic building blocks in digital integrated circuit based designs. Ripple Carry Adder (RCA) gives the most compact design but takes longer computation time. The time critical applications use Carry Look-ahead scheme (CLA) to derive fast results but they lead to increase in area. Carry Select Adder is a compromise between RCA and CLA in term of area and delay. This paper focuses on the design analysis of carry select adder based on Multiplexer using Verilog. The delay (9.970ns) and power (34mW) is minimized. The proposed architecture of carry select adder is simulated in ModelSim6.5b and synthesized in Xilinx ISE14.7.
Keywords
  • Carry select adder,
  • Verilog,
  • Power,
  • delay,
  • Modelsim6.5b,
  • Xilinx ISE14.7
Publication Date
Winter November 17, 2016
DOI
10.9790/4200-0606027781
Publisher Statement
IOSR Journal of VLSI and Signal Processing
Year: 2016 | Volume: 6 | Issue: 6 | Page No.: 77-81


References
B. Ramkumarnd Harish M Kittur, “Low Power and Area Efficient Carry Select Adder” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOL. 20, NO. 2, February 2012.

B. Ramkumar, Kittur, H.M. and Kannan, P. M. (2010) “ASIC Implementation of Modified Faster Carry Save Adder”, Eur. J. Sci. Res., Vol.42, No.1, pp.53–58.

C.S.Manikandababu “An Efficient CSLA Architecture for VLSI Hardware Implementation” IJMIE, ISSN: 2249-0558, Volume 2,ssue 5, 2012, pp.610-622.

Arunprasath S et al., “VLSI Implementation and Analysis of Parallel Adders for Low Power Applications”, International Journal of Computer Science and Mobile Computing, Vol.3 Issue.2, February- 2014, pg. 181-186.

Parmar, Shivani, and Kirat Pal Singh. "Design of high speed hybrid carry select adder." Advance Computing Conference (IACC), 2013 IEEE 3rd International. IEEE, 2013.
CrossRef  |  Direct Link  |  

Citation Information
Somashekhar Malipatil, R. Basavaraju and Praveen kumar Nartam. "Low Power & High Speed Carry Select Adder Design Using Verilog" IOSR Journal of VLSI and Signal Processing Vol. 6 Iss. 6 (2016) p. 77 - 81 ISSN: 2319 – 4197
Available at: http://works.bepress.com/kiratpalsingh/76/
Creative Commons license
Creative Commons License
This work is licensed under a Creative Commons CC_BY-NC International License.