Low Power & High Speed Carry Select Adder Design Using VerilogIOSR Journal of VLSI and Signal Processing (2016)
The binary addition is the basic arithmetic operation in digital circuits and it became essential in most of the digital systems including ALU, microprocessors and DSP. Adders are the basic building blocks in digital integrated circuit based designs. Ripple Carry Adder (RCA) gives the most compact design but takes longer computation time. The time critical applications use Carry Look-ahead scheme (CLA) to derive fast results but they lead to increase in area. Carry Select Adder is a compromise between RCA and CLA in term of area and delay. This paper focuses on the design analysis of carry select adder based on Multiplexer using Verilog. The delay (9.970ns) and power (34mW) is minimized. The proposed architecture of carry select adder is simulated in ModelSim6.5b and synthesized in Xilinx ISE14.7.
- Carry select adder,
- Xilinx ISE14.7
Publication DateWinter November 17, 2016
Citation InformationSomashekhar Malipatil, R. Basavaraju and Praveen kumar Nartam. "Low Power & High Speed Carry Select Adder Design Using Verilog" IOSR Journal of VLSI and Signal Processing Vol. 6 Iss. 6 (2016) p. 77 - 81 ISSN: 2319 – 4197
Available at: http://works.bepress.com/kiratpalsingh/76/
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