Design of an Efficient 16 Bit Vedic Multiplier Using Carry Select Adder with Brent Kung AdderInternational Journal & Magazine of Engineering Technology, Management and Research (2016)
A binary multiplier is an electronic circuit; mostly used in digital electronics, such as a computer, to multiply two binary numbers. It is built using binary adders. In this paper, a high speed and low power 16×16 Vedic Multiplier is designed by using low power and high speed carry select adder. Carry Select Adder (CSA) architectures are proposed using parallel prefix adders. Instead of using dual Ripple Carry Adders (RCA), parallel prefix adder i.e., Brent Kung (BK) adder is used to design Regular Linear CSA. Adders are the basic building blocks in digital integrated circuit based designs. Ripple Carry Adder (RCA) gives the most compact design but takes longer computation time. The time critical applications use Carry Look-ahead scheme (CLA) to derive fast results but they lead to increase in area. Carry Select Adder is a compromise between RCA and CLA in term of area and delay.
Delay of RCA is large therefore we have replaced it with parallel prefix adder which gives fast results. In this paper, structures of 16-Bit Regular Linear Brent Kung CSA, Modified Linear BK CSA, Regular Square Root (SQRT) BK CSA and Modified SQRT BK CSA are designed. This paper presents a technique for N×N multiplication is implemented and gives very less delay for calculating multiplication results for 16×16 Vedic multiplier. Comparisons with existing conventional fast adder architectures have been made to prove its efficiency. The performance analysis shows that the proposed architecture achieves three fold advantages in terms of delay-area-power. The synthesis results of the carry select adders and Vedic multiplier has compared with different conventional techniques.
- Brent Kung (BK) adder,
- Ripple Carry Adder (RCA),
- Regular Linear Brent Kung Carry Select Adder,
- Modified Linear BK Carry Select Adder,
- Regular Square Root (SQRT) BK CSA and Modified SQRT BK CSA; Vedic Multiplier
Publication DateSummer September 30, 2016
Citation InformationDasari Rudrama and Inala Raghava Krishna. "Design of an Efficient 16 Bit Vedic Multiplier Using Carry Select Adder with Brent Kung Adder" International Journal & Magazine of Engineering Technology, Management and Research Vol. 3 Iss. 9 (2016) p. 840 - 846 ISSN: 2348-4845
Available at: http://works.bepress.com/kiratpalsingh/75/
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