Skip to main content
Implementation of 32-Bit Carry Select Adder using Brent-Kung Adder
Indian Journal of Science and Technology (2016)
  • P. Nithin, SRKR Engineering College, Bhimavaram
  • N. Udaya Kumar, SRKR Engineering College, Bhimavaram
  • K. Bala Sindhuri, SRKR Engineering College, Bhimavaram
The circuit used to add the two numbers or two bits is adder. The main problem with the adder is both the area and delay to produce the final output. So, this paper implements an adder it requires a less amount of delay and area to produce the final output. The reduction of delay and area is done by the Parallel Prefix Adders. It plays a prominent role in Digital Combinational Circuits. Area and power are other factors which really makes the adder effective. The techniques used to get a less amount of delay and area is by using the Binary-to-Excess-1 Converter (BEC) and a Parallel Prefix Adder. The delay of the Modified Linear Carry Select Adder of Brent Kung Adder is less when compared with the Regular Carry Select Adder architecture. The delay and area further can be improved by using a Square root Carry Select adder. This paper focuses on operation of Parallel Prefix Adders of 32 bit Brent-Kung Adder.
  • And-Or-Inverter (AOI) Logic,
  • Binary-to-Excess-1 Converter (BEC),
  • Brent-Kung (BK) Adders,
  • Carry Select Adder (CSLA),
  • Parallel Prefix Adder
Publication Date
Winter November 17, 2016
Publisher Statement
Indian Journal of Science and Technology
Year: 2016 | Volume: 5 | Issue: 9 | Page No.: 1-7

Parmar, Shivani, and Kirat Pal Singh. "Design of high speed hybrid carry select adder." Advance Computing Conference (IACC), 2013 IEEE 3rd International. IEEE, 2013.
CrossRef  |  Direct Link  | 

Snir M. Depth-size trade-offs for parallel prefix computation.Journal of Algorithms. 1986 Jun; 7(2):185–201.

Jackson DJ, Hannah SJ. Modeling and comparison of adder designs with Verilog HDL. 25th South-eastern Symposium on System Theory; 1993 Mar. p. 406–10.

Wei BWY, Clark D. Thompson CD. Area-time optimal adder design. IEEE Transactions on Computers. 1967 May; 39:666–75.

Ramkumar B, Kittur HM. Low-power and area-efficient carry select adder. IEEE Transaction on Very Large Scale Integration Systems. 2012 Feb; 20(2):371–5.

Rabaey JM. Digital integrated circuits - A design perspective. New Jersey: Prentice-Hall; 2001.

Brent R, Kung H. A regular layout for parallel adders.IEEE Transaction on Computers. 1982 Mar; C-31(3): 260–4.

Siliveru A, Bharathi M. Design of Kogge-Stone and Brent- Kung Adders using degenerate pass transistor logic. International Journal of Emerging Science and Engineering.2013 Feb; 1(4):38–41.

Ramkumar B Kittur HM, Kannan PM. ASIC implementation of modified faster carry save adder. Eur J Sci Res. 2010; 42(1):53–8.

BalaSindhuri K, PadmaVasavi K, Santi Prabha I, Udaya Kumar N. VLSI architecture for linear Carry Select Adder with zero finding. 6th International Advanced Cloud Computing Conference IACC; 2016.
Citation Information
P. Nithin, N. Udaya Kumar and K. Bala Sindhuri. "Implementation of 32-Bit Carry Select Adder using Brent-Kung Adder" Indian Journal of Science and Technology Vol. 9 Iss. 44 (2016) p. 1 - 7 ISSN: 0974-6846
Available at:
Creative Commons license
Creative Commons License
This work is licensed under a Creative Commons CC_BY-NC International License.