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Design of a High Speed 32-Bit Parallel Hybrid Adder for Digital Arithmetic System
International Journal for Research in Applied Science & Engineering Technology (2016)
  • Vaibhav V. Deshmukh
  • Dr. Nitiket N. Mhala
Addition is a heavily used basic fundamental arithmetic operation that figures prominently in any digital logic system, digital signal processor, control system and scientific applications. Addition is a very hardware intensive subject and one as users are mostly concerned with getting low smaller area and higher speed. In ALU, adders play a major role not only in addition but it also performing many other basic arithmetic operations like subtraction, multiplication, etc. Hence, realization of an efficient adder is required for better performance of an ALU and therefore the processor. This paper presents the design of 32-bit Parallel Hybrid Adder architectures consists of Ripple Carry Adder, Carry Look Ahead Adder and Carry Select Adder. The time delay and area have been analyzed. Results will show the variation of area and speed for different designs. The designed adder consists of parallel implementation of 8-bit Ripple Carry Adder and 8-bit Carry Look Ahead Adder together to form 32-bit Parallel Hybrid Adder. The 32-bit Parallel Hybrid Adder is synthesized for XC3S1600 of Spartan-3E FPGAs implemented in 90nm technology.
  • Area Efficient,
  • CLA,
  • CSA,
  • Low Propagation Delay,
  • RCA
Publication Date
Summer July 28, 2016
Publisher Statement
International Journal for Research in Applied Science & Engineering Technology
Year: 2016 | Volume: 4 | Issue: 7 | Page No.: 181-187

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Citation Information
Vaibhav V. Deshmukh and Nitiket N. Mhala. "Design of a High Speed 32-Bit Parallel Hybrid Adder for Digital Arithmetic System" International Journal for Research in Applied Science & Engineering Technology Vol. 4 Iss. 7 (2016) p. 181 - 187 ISSN: 2321-9653
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