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Comparison of 32-Bit Hybrid Adders in VHDL
Journal of Emerging Technologies and Innovative Research (2016)
  • Viraj V. Gotmare, GHRAET, Nagpur, Maharashtra, India
  • Dr. Pankaj Agrawal, GHRAET, Nagpur, Maharashtra, India
This paper describes the comparison between the hybrid adders. Adders are always used in many data-processing systems to perform fast arithmetic operations. The carry select adder (CSA) is a high speed adder. It provides good compromise between RCA and CLA. The ripple carry adder (RCA) has a most compact design but it takes longer computation time. The time critical applications uses carry look-ahead adder (CLA) to derive fast result but it required a large area. In this work we compared hybrid adders on the basis of delay, power and area. This design has been synthesized by Spartan 3 family with XC3S400 device.
  • Adder,
  • carry select adder,
  • Ripple carry adder,
  • Carry look-ahead adder,
  • VHDL code
Publication Date
Summer June 15, 2016
Publisher Statement
Journal of Emerging Technologies and Innovative Research
Year: 2016 | Volume: 3 | Issue: 6 | Page No.: 107-109

V. Kokilavani, K. Preethi,and P. Balasubramanian, ―FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders‖ Hindawi Publishing Corporation Advances in Electronics Volume 2015, Article ID 713843.

Basant Kumar Mohanty, Senior Member, IEEE, and Sujit Kumar Patel, ―Area– Delay–Power Efficient Carry-Select Adder‖ IEEE Transaction on circuits and systems— II: express briefs , vol .61, no.6, Jun 2014.

Parmar, Shivani, and Kirat Pal Singh. "Design of high speed hybrid carry select adder." Advance Computing Conference (IACC), 2013 IEEE 3rd International. IEEE, 2013.
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K. Preethi,and P. Balasubramanian, ―FPGA Implementation of Synchronous section-carry base carry look-ahead adder‖ 2nd International conference on devices, circuits and systems (ICDCS), 2014 IEEE

Shamim Akhter, Saurabh Chaturvedi, Kilari Pardhasardi, ―CMOS implementation of efficient 16 bit square root carry select adder‖ 2nd International Conference on Signal Processing and Integrated Networks (SPIN), 2015 IEEE

J.Monteiro, J. L. G¨untzel, and L. Agostini, ―A1CSA: an energy efficient fast adder architecture for cell-based VLSI design,‖ in Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 11), pp. 442–445, Beirut, Lebanon, December 2011.
Citation Information
Viraj V. Gotmare and Pankaj Agrawal. "Comparison of 32-Bit Hybrid Adders in VHDL" Journal of Emerging Technologies and Innovative Research Vol. 3 Iss. 6 (2016) p. 107 - 109 ISSN: 2349-5162
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This work is licensed under a Creative Commons CC_BY-NC International License.