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Review of 5 stage Pipelined Architecture of 8 Bit Pico Processor
International Journal of Electronics, Communication & Soft Computing Science and Engineering (2014)
  • Shankar Kumar Mishra
  • Dr. Nisha P Sarwade
Abstract
Proposed paper is the study of unpipelined architecture of a 8 bit Pico Processor (pP) [3][4] and how its overall
through put can be increased by implementing pipelining. Pico processor is an 8 bit processor which is similar to 8 bit microprocessors for small embedded applications and it is intended for educational purpose .In the past un pipelined single cycle and multi cycle Pico Processor is implemented [3] .Its speed and overall through put can be increased by implementation of pipeline architecture [1] so that it can be used in small embedded applications like gaming processor.
Keywords
  • Pico Processor,
  • VHDL,
  • RISC,
  • Pipeline.
Publication Date
Summer June 26, 2014
Citation Information
Shankar Kumar Mishra and Nisha P Sarwade. "Review of 5 stage Pipelined Architecture of 8 Bit Pico Processor" International Journal of Electronics, Communication & Soft Computing Science and Engineering Vol. 3 Iss. 4 (2014) p. 8 - 11 ISSN: 2277-9477
Available at: http://works.bepress.com/kiratpalsingh/64/
Creative Commons license
Creative Commons License
This work is licensed under a Creative Commons CC_BY-NC International License.