Skip to main content
profile image
Selected Works of Karthikeyan Umapathy
Contribution to Book
FPGA Implementation of Parallel Adder Using Reversible Logic Gates
(2021)
  • S. A. Yuvaraj
  • K. Gunasekaran
  • D. Muthukumaran
  • K. Umapathy
Link
Disciplines
Publication Date
January 1, 2021
DOI
10.1007/978-981-33-4687-1_40
Citation Information
S. A. Yuvaraj, K. Gunasekaran, D. Muthukumaran and K. Umapathy. "FPGA Implementation of Parallel Adder Using Reversible Logic Gates" (2021) p. 429 - 435
Available at: http://works.bepress.com/karthikeyan_umapathy/23/