In this paper, the electrical performance of the test patterns used in the de-embedding method for TSV characterization was studied thoroughly. For all test patterns, full wave models were built and then analyzed based on simulated electrical performances. Equivalent circuit model analysis and parametric study results of the test patterns further demonstrate the accuracy of the full wave models. Furthermore, Scanning Electron Microscopy (SEM) measurements were taken for all the test patterns, and full wave models were optimized based on the measured dimensions. Finally, the response of the TSV pair was obtained by de-embedding the pads and traces from the TSV pair simulation with the test fixtures. Good agreement between the de-embedded results with analytical characterization and the full-wave simulation for a single TSV pair was achieved.
- Electric network analysis,
- Electromagnetic compatibility,
- Electronics packaging,
- Equivalent circuits,
- Integrated circuit manufacture,
- Optimization,
- Reconfigurable hardware,
- Scanning electron microscopy,
- Analytical characterization,
- De-embedding,
- Electrical performance,
- Equivalent circuit model,
- Full waves,
- Full-wave simulations,
- Silicon interposers,
- Through-Silicon-Via (TSV),
- Three dimensional integrated circuits,
- analytical solution,
- circuit analysis,
- SEM measurement
Available at: http://works.bepress.com/jun-fan/53/