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Article
An FPGA based implementation of CA-CFAR processor
Asian Journal of Information Technology (2007)
  • Thamir R. Saeed, Department of Electrical Engineering, University of Technology, Iraq
  • Jawad K. Ali, Department of Electrical Engineering, University of Technology, Iraq
  • Ziad T. Yassen, Department of Electrical Engineering, University of Technology, Iraq
Abstract
In this study, a constant false alarm rate processor is investigated and a special focusing is devoted to the cell-average constant false alarm rate (CA-CFAR) processor. This processor is analyzed and its performance is estimated. An FPGA-based CA-CFAR processor has been implemented using Xilinx integrated circuit chip XC9600. The implemented processor using this technique has been tested with signals imbedded with different types of clutter and noise-alike signals. The implementation process and the processor response reflect how this digital tool is excellent due to its high reliability and flexibility.
Publication Date
2007
Citation Information
Thamir R. Saeed, Jawad K. Ali and Ziad T. Yassen. "An FPGA based implementation of CA-CFAR processor" Asian Journal of Information Technology Vol. 6 Iss. 4 (2007) p. 511 - 514
Available at: http://works.bepress.com/jawad_ali/49/