A CMOS Time to Digital Converter IC with 2 Level Analog CAMDepartmental Papers (ESE)
AbstractA time to charge converter IC with an analog memory unit (TCCAMU) has been designed and fabricated in HP's CMOS 1.2-µm n-well process. The TCCAMU is an event driven system designed for front end data acquisition in high energy physics experiments. The chip includes a time to charge converter, analog Level 1 and Level 2 associative memories for input pipelining and data filtering, and an A/D converter. The intervals measured and digitized range from 8-24 ns. Testing of the fabricated chip resulted in an LSB width of 107 ps, a typical differential nonlinearity of < 35 ps, and a typical integral nonlinearity of < 200 ps. The average power dissipation is 8.28 mW per channel. By counting the reference clock, a time resolution of 107 ps over ~ 1 s range could be realized.
Document TypeJournal Article
Date of this Version9-1-1994
- time to charge converter,
- associative memory
Citation InformationEric J. Gerds, Jan Van der Spiegel, Rick Van Berg, Hugh H. Williams, et al.. "A CMOS Time to Digital Converter IC with 2 Level Analog CAM" (1994)
Available at: http://works.bepress.com/jan_vanderspiegel/28/