Estimates of power consumed by an IC are useful not only for handling thermal issues, but also for predicting power- and signal-integrity issues, since variations in power on a clock-by-clock basis can be used to estimate power-bus noise. Estimation of clock-by-clock power consumption is challenging, however, because full vectored simulation is computationally intensive and traditional vectorless techniques only estimate the average power over many clock cycles. Methods are presented to estimate the statistical variation of power consumed on a clock-by-clock basis. Estimates of the mean and standard deviation of power are compared to results of Monte Carlo simulations performed using VHDL and Altera's Quartus II PowerPlay Power Analysis tools.