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Article
Evaluation Scheme for NoC based CMP with Integrated Processor Management System
International Journal of Electronics and Telecommunications
  • Dawid Maksymilian Zydek, University of Nevada, Las Vegas
  • Henry Selvaraj, University of Nevada, Las Vegas
  • Leszek Koszalka, Wrocław University of Technology
  • Iwona Pozniak-Koszalka, Wrocław University of Technology
Document Type
Article
Publication Date
9-16-2010
Abstract
With the opportunities and benefits offered by Chip Multiprocessors (CMPs), there are many challenges that need to be addressed in order to exploit the full potential of CMPs. Such aspects as parallel programs, interconnection design, cache arrangement and on-chip cores allocation become a limiting factor. To ensure validity of approaches and research, we propose an evaluation system for CMPs with Network-on-Chip (NoC) and processor management system integrated on one die. The suggested experimentation system is described in details. The proposed system that is used for tests and results of the experiments are presented and discussed. As decision making criteria, we consider energy efficiency of Processor Allocator (PA) and NoC, as well as NoC traffic characteristic (load balance). In order to improve the system understanding, brief overview on most important NoC and PA architectures is also presented. Analyzed results reveal that CMP with a PA controlled by IFF allocation algorithm for mesh systems and torus-based NoC driven by DORLB routing with express-virtual-channel flow control achieved the best traffic balance and energy characteristic.
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Citation Information
Dawid Maksymilian Zydek, Henry Selvaraj, Leszek Koszalka and Iwona Pozniak-Koszalka. "Evaluation Scheme for NoC based CMP with Integrated Processor Management System" International Journal of Electronics and Telecommunications (2010) p. 157 - 168
Available at: http://works.bepress.com/henry_selvaraj/26/