Skip to main content
Presentation
Target Environment Simulation and its Impact on ArchitectureValidation
MTV ’13 Proceedings of the 2013 14th International Workshop on Microprocessor Test and Verification
  • Jack L Mason, Nova Southeastern University
  • Gregory Simco, Nova Southeastern University
Presentation Date
12-13-2014
Document Type
Conference Proceeding
Description

Due to simulation overhead, validation of proposed microarchitecture enhancements may be limited to simple test scenarios, which focus on the known architectural deficiencies. These test scenarios often avoid a complete simulation of the eventual target environment in which the enhancements will be employed. A case study is presented, comparing and contrasting the performance of previous Thread-Level Speculation (TLS) proposals with that of a new, context-preserving proposal. Validation is performed within the constraints of a simulated target environment.

DOI
10.1109/MTV.2013.27
Comments

Conference held in Austin, TX, December 11-13, 2013

Disciplines
Citation Information
Jack L Mason and Gregory Simco. "Target Environment Simulation and its Impact on ArchitectureValidation" MTV ’13 Proceedings of the 2013 14th International Workshop on Microprocessor Test and Verification (2014) p. 74 - 76 ISSN: 1550-4093
Available at: http://works.bepress.com/greg-simco/21/