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Engineering Nanowire n-MOSFETs at L-g < 8 nm
IEEE TRANSACTIONS ON ELECTRON DEVICES
  • Saumitra Mehrotra, Birck Nanotechnology Center, Network for Computational Nanotechnology, Purdue University
  • SungGeun Kim, Birck Nanotechnology Center, Network for Computational Nanotechnology, Purdue University
  • Tillmann Kubis, Birck Nanotechnology Center, Network for Computational Nanotechnology, Purdue University
  • Michael Povolotskyi, Birck Nanotechnology Center, Network for Computational Nanotechnology, Purdue University
  • Mark S. Lundstrom, Birck Nanotechnology Center, Network for Computational Nanotechnology, Purdue University
  • Gerhard Klimeck, Birck Nanotechnology Center, Network for Computational Nanotechnology, Purdue University
Abstract
As metal-oxide-semiconductor field-effect transistors (MOSFETs) channel lengths (L-g) are scaled to lengths shorter than L-g < 8 nm source-drain tunneling starts to become a major performance limiting factor. In this scenario, a heavier transport mass can be used to limit source-drain (S-D) tunneling. Taking InAs and Si as examples, it is shown that different heavier transport masses can be engineered using strain and crystal-orientation engineering. Full-band extended device atomistic quantum transport simulations are performed for nanowire MOSFETs at L-g < 8 nm in both ballistic and incoherent scattering regimes. In conclusion, a heavier transport mass can indeed be advantageous in improving ON-state currents in ultrascaled nanowire MOSFETs.
Keywords
  • InAs; nanowire; quantum transport; Si; source-drain tunneling; strain; tight-binding (TB) approach; ELECTRONICS; FETS
Date of this Version
7-1-2013
DOI
10.1109/TED.2013.2263806
Citation Information
Saumitra Mehrotra, SungGeun Kim, Tillmann Kubis, Michael Povolotskyi, et al.. "Engineering Nanowire n-MOSFETs at L-g &lt; 8 nm" IEEE TRANSACTIONS ON ELECTRON DEVICES (2013)
Available at: http://works.bepress.com/gerhard_klimeck/85/