Majority-logic decoding is attractive for three reasons: (1) It can be simply implemented; (2) the decoding delay is short; and (3) its performance, while suboptimal, is always superior to bounded distance decoding. For these reasons, majority-logic decodable cyclic codes are very suitable for error control in high speed digital data transmission systems. Among the majority-logic decodable codes, the one-step decodable codes can be most easily implemented; they employ a single majority-logic gate. In this paper we study a class of one-step majority-logic decodable cyclic codes. First, we describe these codes in a simple manner. Second, a way of finding the orthogonal polynomials for decoding these codes is presented. Third, we show that for a given error correction capability, the ratio of the number of parity digits to the code length goes to zero as the code length increases. For error correction capabilities of the form 2k-1 or 2k, we determine the dimensions of the codes exactly.