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Article
Preprocessing Strategy for Effective Modulo Scheduling on Multi-Issue Digital Signal Processors
Proceedings of the 16th International Conference on Compiler Construction, March 2007, Braga, Portugal
  • Doosan Cho, Seoul National University
  • Ravi Ayyagari, Boise State University
  • Gang-Ryung Uh, Boise State University
  • Yunheung Paek, Seoul National University
Document Type
Conference Proceeding
Publication Date
3-1-2007
Disciplines
Abstract
To achieve high resource utilization for multi-issue Digital Signal Processors (DSPs), production compilers commonly include variants of the iterative modulo scheduling algorithm. However, excessive cyclic data dependences, which exist in communication and media processing loops, often prevent the modulo scheduler from achieving ideal loop initiation intervals. As a result, replicated functional units in multi-issue DSPs are frequently underutilized. In response to this resource underutilization problem, this paper describes a compiler preprocessing strategy that capitalizes on two techniques for effective modulo scheduling, referred to as cloning1 and cloning2. The core of the proposed techniques lies in the direct relaxation of cyclic data dependences by exploiting functional units which are otherwise left unused. Since our preprocessing strategy requires neither code duplication nor additional hardware support, it is relatively easy to implement in DSP compilers. The strategy proposed has been validated by an implementation for a StarCore SC140 optimizing C compiler.
Citation Information
Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh and Yunheung Paek. "Preprocessing Strategy for Effective Modulo Scheduling on Multi-Issue Digital Signal Processors" Proceedings of the 16th International Conference on Compiler Construction, March 2007, Braga, Portugal (2007)
Available at: http://works.bepress.com/gang-ryung_uh/9/