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Experience with a Retargetable Compiler for a Commercial Network Processor
Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems, October 2002, Grenoble, France
  • Jinhwan Kim, Korea Advanced Institute of Science & Technology
  • Sungjoon Jung, Korea Advanced Institute of Science & Technology
  • Yunheung Paek, Korea Advanced Institute of Science & Technology
  • Gang-Ryung Uh, Boise State University
Document Type
Conference Proceeding
Publication Date
10-1-2002
Disciplines
Abstract
The Paion PPII network processor is designed to meet the growing need for new high bandwidth network equipment. In order to rapidly reconfigure the processor for frequently varying internet services and technologies, a high performance compiler is urgently needed. Albeit various code generation techniques have been proposed for DSPs or ASIPs, we experienced these techniques are not easily tailored towards the target Paion PPII processor due to striking architectural differences. First, we will show the architectural challenges posed by the target processor. Second, novel compiler techniques will be described that effectively exploit unorthogonal architectural features. The techniques include virtual data path, compiler intrinsics, and interprocedural register allocation. Third, intermediate benchmark results will be presented to demonstrate the effectiveness of our techniques.
Citation Information
Jinhwan Kim, Sungjoon Jung, Yunheung Paek and Gang-Ryung Uh. "Experience with a Retargetable Compiler for a Commercial Network Processor" Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems, October 2002, Grenoble, France (2002)
Available at: http://works.bepress.com/gang-ryung_uh/6/