Skip to main content
Improving Processor Efficiency by Statically Pipelining Instructions
ACM Sigplan Notices, LCTES '13
  • Ian Finlayson, University of Mary Washington
  • Brandon Davis, Florida State University
  • Peter Gavin, Florida State University
  • Gang-Ryung Uh, Boise State University
  • David Whalley, Florida State University
  • Magnus Själander, Florida State University
  • Gary Tyson, Florida State University
Document Type
Conference Proceeding
Publication Date
A new generation of applications requires reduced power consumption without sacrificing performance. Instruction pipelining is commonly used to meet application performance requirements, but some implementation aspects of pipelining are inefficient with respect to energy usage. We propose static pipelining as a new instruction set architecture to enable more efficient instruction flow through the pipeline, which is accomplished by exposing the pipeline structure to the compiler. While this approach simplifies hardware pipeline requirements, significant modifications to the compiler are required. This paper describes the code generation and compiler optimizations we implemented to exploit the features of this architecture. We show that we can achieve performance and code size improvements despite a very low-level instruction representation. We also demonstrate that static pipelining of instructions reduces energy usage by simplifying hardware, avoiding many unnecessary operations, and allowing the compiler to perform optimizations that are not possible on traditional architectures.
Citation Information
Ian Finlayson, Brandon Davis, Peter Gavin, Gang-Ryung Uh, et al.. "Improving Processor Efficiency by Statically Pipelining Instructions" ACM Sigplan Notices, LCTES '13 (2013)
Available at: